Learn RISC-V.
An open, royalty-free instruction set architecture that's reshaping how processors are designed. Everything you need to get started — lessons, videos, simulators, and a structured course — collected in one place.
01 — Getting started
Your learning path.
If you plan to learn how to use the ISA, you are at the right place. We have developed lessons, tutorials, and tools that help you learn at your own pace. With a little dedication and effort, you can begin your journey to using RISC-V and develop your own RISC-V-based hardware or software projects.
Before you begin
This curriculum assumes you have:
- A basic understanding of computer architecture and digital logic design.
- Familiarity with Verilog — see our Verilog tutorial (PDF).
- Comfort with assembly language at a conceptual level.
The three-step journey
Read the lessons
Start with the reading list — foundational papers and references that ground you in the ISA.
Watch the tutorials
Reinforce the lessons with visual, interactive video walkthroughs.
Practice with tools
Get hands-on with simulators and emulators — write code and run programs, no hardware required.
02 — Tutorial videos
Watch and follow along.
These tutorial videos cover the basics of RISC-V, setting up a development environment, writing and compiling RISC-V code, and using RISC-V tools and simulators. They're especially helpful if you prefer visual, interactive learning.
03 — Reading list
Recommended materials.
RISC-V application-oriented research papers, academic articles, and technical publications — from novel architectural features to performance, security, and software-development frameworks.
- The BRISC-V Platform: A Practical Teaching Approach for Computer Architecture
- Ripes: A Visual Computer Architecture Simulator
- RISC-V Console: A Containerized RISC-V Based Game Console Emulator for Education
- WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment
- About Virgule and its simulator emulsiV
04 — Tools & simulators
Hands-on with the ISA.
Learning tools to help you design, develop, and optimize RISC-V-based systems — simulators and emulators let you test designs without physical hardware. Once you've read the basics, the fastest way to internalize RISC-V is to run code on it.
Trireme
A parameterized, synthesizable set of modules for design exploration with the RISC-V ISA. Everything needed to bring up custom RISC-V hardware and software, from low-power microcontrollers to multi-core processors.
Ripes
A visual computer architecture simulator built around the RISC-V ISA, integrating a built-in assembler, compiler support, and cache simulator around a visual microarchitecture model.
emulsiV
A visual simulator for Virgule, a minimal RISC-V CPU core. Shows the datapath structure and animates data transfers step by step — built for teaching the basics of computer architecture.
WebRISC-V
A web-based graphical pipelined-datapath simulation environment for teaching how assembly executes on the RISC-V pipeline and illustrating the pipeline architectural elements.
RISC-V Console
A simulator for a hypothetical RISC-V-based game console, with Dockerfiles to build the toolchain for firmware and game development. Developed for UC Davis CS courses.
RISC-V Interpreter
A simple, browser-based RISC-V interpreter from Cornell University — step through instructions and watch register and memory state update.
Questions?
Get in touch.
Working through the curriculum and have a question? Hit reply — we'll do our best to help.